1. Field of the Invention
The present invention relates to an apparatus for detecting synchronization by detecting a synchronization pattern from data demodulated by a demodulating unit in which a pseudo lock can occur, and a method thereof.
2. Description of the Related Art
Conventionally, there is a system for digital-modulating/demodulating and transmitting data. The receiving side of this system demodulates a received signal in a demodulating unit, and detects synchronization (takes synchronization) by detecting a synchronization pattern from the demodulated data.
For example, assume that one frame of transmission data is configured by eight packets each of which is composed of 204 bytes, the first byte of the first packet is a synchronization byte “B8”, and the first bytes of the remaining 7 packets are respectively “47” as shown in FIG. 1. In this case, taking synchronization means the detection, from demodulated data, of the beginning of a frame by recognizing a pattern of synchronization bytes such as “B8”, “47”, “47”, . . . .
If the synchronization byte “B8” shown in (a) can be detected when the transmission data shown in FIG. 1 is obtained as demodulated data, the synchronization byte subsequently exists every 204 bytes. Therefore, frame synchronization can be taken and no problems are posed if the synchronization byte continues to be detected.
However, the values “B8” and “47”, which are the synchronization bytes, naturally exist also as data. Accordingly, if “B38” shown in (b) is detected as a synchronization byte, the synchronization byte “47” does not exist after 204 bytes from “B38”, leading to a detection miss of the synchronization byte. Therefore, the recognition of the pattern of synchronization bytes is remade from scratch. Additionally, even if the recognition is remade from scratch, the byte detected next as the synchronization byte is not always the normal synchronization byte, which can possibly cause the repetition of a detection miss of the synchronization byte.
Thus, Patent Document 1 (Japanese Patent Publication No. 2001-057549) proposes an apparatus for preventing the recognition of a pattern of synchronization bytes from being remade from scratch at a time point when a detection miss of a synchronization byte occurs, by providing a plurality of synchronization state machines each of which does not detect the same position of a synchronization byte.
As a factor to delay frame synchronization, an occurrence of pseudo lock is cited. The pseudo lock is a phenomenon that a carrier reproduction loop within a demodulating unit locks in a pseudo manner in a state where a phase shifts in units of 90° such as 90°, 180°, or 270° relative to an expected value.
One example of the pseudo lock in a case where a phase shifts in units of 90° every one symbol is described with reference to FIG. 2. The example shown in this figure is an example of the case of QPSK (Quadrature Phase Shift Keying).
Here, assume that data “0” exists in the first quadrant in a normal lock state as shown on an IQ (I: In phase, Q: Quadrature phase) plane of the upper left of FIG. 2. In this case, the data “0”, which should originally exist in the first quadrant, moves to the second quadrant as shown on the IQ plane of the upper right of FIG. 2 if the phase shifts by 90° (rotates by 90° in the counterclockwise direction) after one symbol. If the phase further shifts by 90° after the next one symbol (after two symbols), the data “0”, which should originally exist in the first quadrant, moves to the third quadrant as shown on the IQ plane of the lower right of FIG. 2. If the phase still further shifts by 90° after the next one symbol (after 3 symbols), the data “0”, which should originally exist in the first quadrant, moves to the fourth quadrant as shown on the IQ plane of the lower left of FIG. 2. Then, if the phase still further shifts by 90° after the next one symbol (after 4 symbols), the data “0” restores to the original state. Thereafter, this state transition is repeated every one symbol. Even if the phase shifts by 90°, 180° (90°×2), or 270° (90°×3) relative to an expected value as described above, it is determined that the normal lock occurs in the demodulating unit. This is because the position where the symbol point exists does not shift although its data differs. However, in this example, the data in the first quadrant makes a transition of “0”→“3”→“2”→“1” every one symbol. Accordingly, it cannot be expected that the synchronization bytes “B38” and “47” are not normally output from the demodulating unit, which naturally leads to unsuccessful frame synchronization.
In the meantime, in a case of QAM (Quadrature Amplitude Modulation), multilevel data is represented by the amplitudes (levels) of I and Q axes as in the case of 16QAM shown in FIG. 3. For example, if the amplitudes of I and Q are respectively 2, 3 is presented as data.
Here, an example of a case of 16QAM, in which a phase shifts in units of 90° every one symbol, is described with reference to FIGS. 3 and 4 as another example of the pseudo lock.
Originally, one packet is configured by a synchronization byte and data. Here, explanation is provided by assuming that one packet is configured only by a synchronization byte for ease of explanation. Additionally, although the synchronization byte in the above description is configured by 8 bits such as “B38” and “47”, the synchronization byte is assumed to be configured only by low-order 4 bits here.
In FIG. 4, in a normal lock state, when the synchronization byte is output in accordance with a symbol clock, normal synchronization bytes are output as shown in “normal lock” in this figure, and frame synchronization successfully completes.
However, since the phase rotates in the pseudo lock state as describe above, values like expected values are not output, and those shown in the “pseudo lock” in this figure are output.
Here, assume that data “8” is output in the pseudo lock state when I and Q are −1 and 1 respectively on the symbol clock (1). In this case, I and Q become 2 and −2 respectively, and data “7” is output on the symbol clock (2) in the normal lock state, whereas I and Q become 2 and 2 respectively due to the phase rotated by 90° in the counterclockwise direction, and data “3” is output in the pseudo lock state.
Additionally, on the symbol clock (3), I and Q become 2 and −2 respectively and data “7” is originally output in the normal lock state, but the phase further rotates by 90° in the counterclockwise direction, and I and Q become −2 and 2 respectively, and data “B” is output in the pseudo lock state. At this time, the phase shifts by 180°, because it proceeds by 2 clocks from the original position of “7”.
Furthermore, on the symbol clock (4), I and Q become 2 and −2 respectively and data “7” is output in the normal lock state, but the phase still further rotates by 90° in the counterclockwise direction, and I and Q become −2 respectively, and data “F” is output in the pseudo lock state. At this time, the phase shifts by 270°, because it proceeds by 3 clocks from the original position of “7”.
On the symbol clock (5), the phase comes full circle, and restores to the original position. Therefore, I and Q become 2 and −2 respectively, and data “7” is output.
Since data output from the demodulating unit is destroyed in the pseudo lock state as described above, frame synchronization cannot be taken as it is.
Accordingly, a conventional process for once releasing a lock and for making a lock again occur is performed with a predetermined control, if pseudo lock occurs and frame synchronization cannot be taken within a predetermined time period.
Additionally, for frame synchronization enabled to be taken in a shorter time, by way of example, Patent Document 2 (Japanese Patent Publication No. 2000-278344) proposes a quadrature phase demodulating circuit, which detects pseudo lock by detecting that a carrier reproduction loop is locked and a frame of a baseband signal is asynchronous, in order to quickly detect an occurrence of the pseudo lock.
However, when the pseudo lock once occurs, the process for once releasing a lock and for making a lock again occur is conventionally performed as described above. Therefore, the process is again performed, which causes a wasteful overhead. Furthermore, there is no guarantee that the normal lock state occurs next.